1.25gbps fiber-optic vcsel/laser driver CS6706 block diagram general description century semiconductor inc. features applications usa: 1485 saratoga ave. #200 san jose, ca, 95129 tel: 408-973-8388 fax: 408-973-9388 sales@century-semi.com sales@century-semi.com.tw www.century-semi.com rev.1.2 august 2001 page 1 of 8 century semiconductor, inc. taiwan: no. 2, industry east rd. 3rd, science-based industrial park, hsin-chu, taiwan tel: 886-3-5784866 fax: 886-3-5784349 the CS6706 is a high-speed fiber optic vcsel driver suited for applications up to 1.25gbps. the CS6706 accepts differential pecl inputs, and includes a cmos disable pin for bias and modulation current control. further, the bias and modulation current can be set independently via two external resistors, and the rise/fall time can also be adjusted using external resistors. a monitor photodiode can be incorporated in the application circuit to ensure a stable laser power source. any failure of the laser is detected using the two on-chip window comparators. once a failure is detected, the laser power safety switch will be triggered and can only be reset by a power off condition. the slow start feature allows bias current to settle before modulation current output begins, to protect the laser. ? rise/fall time < 200ps, ideally suited for application up to 1.25gbps. ? independently programmable laser bias and mod- ulation current: bias current to 60ma and modula- tion current to 45ma. ? differential pecl inputs. ? automatic laser power control with monitor circuit. ? slow start and safety switch. ? laser failure indication. ? programmable rise/fall time. ? supports both 3.3 and 5 volt operation. ? available as die or tssop-20 package. dinn dinp predriver modp dcb ixmt modn rofs rmod rdcb current modulation set bias set output driver disable ibias fail rise/fall set auto power set delay start bandgap amplifier control logic dcbias driver basfb rpin verf start v dd -1.6v failtgr v dd -2.4v pin CS6706 buffer ? fddi ? fiber channel 100 ? sonet oc-12/oc-24 ? fast ethernet ? gigabit ethernet ? vcsel driver transmitters
CS6706 century semiconductor inc. page 2 of 8 die connection diagram figure-1 pin connection diagram (tssop-20) figure-2 tssop-20 v ss v ss v ss v ss rofs modn 1.473 mm 1.357 mm 2 3 4 4 5 91011 14 16 16 17 19 20 modp vref rmod v dd v dd dinp dinn start disable rdcb bsfb pin v dd v dd v ss 6 7 8 12 12 13 13 3 1 18 15 rpin v ss fail dcb 1 2 3 4 5 6 7 8 9 10 start disable fail modp v sso modn dcb v ssa v dda pin dinn dinp v dd v ss vref rmod rofs rpin rdcb basfb 20 19 18 17 16 15 14 13 12 11 CS6706
CS6706 century semiconductor inc. page 3 of 8 pin description name pin description dinn 1 inverse differential data input pin. ac-couple or direct couple to differential pecl source. dinp 2 differential data input pin. ac-couple or direct couple to differential pecl source. v dd 3 input section power pin. connect to most positive supply voltage. v ss 4 input section ground pin. connect to most negative supply voltage. vref 5 reference voltage output pin (about 1.8v). connect a capacitor between this pin and ground. rmod 6 modulation current set point input pin. connect a resistor between this pin and ground. rofs 7 rise/fall time set point input pin. connect a resistor between this pin and ground. rpin 8 input pin for automatic power control circuit. connect a resistor between this pin and ground. rdcb 9 bias current set point pin. connect a resistor between this pin and ground. basfb 10 bias current set point pin. connect this pin to rdcb for automatic power control. disconnecting basfb and rdcb will disable the automatic power control function. pin 11 monitor diode current control input pin. connect a capacitor between this pin and ground. v dda 12 output section power pin. connect to most positive supply voltage. v ssa 13 output section ground pin. connect to most negative supply voltage. dcb 14 laser dc bias current pin. modn 15 inverse driver output stage pin. see application circuit schematic. v sso 16 output section ground pin. connect to most negative supply voltage. modp 17 driver output stage pin. see application circuit schematic. fail 18 laser failure indication pin. disable 19 disable input pin (cmos logic). logic high to disable laser and modulation current. on-chip pull- down. start 20 slow start for laser drive pin. connect a capacitor between this pin and ground.
CS6706 century semiconductor inc. page 4 of 8 absolute maximum ratings recommended operating conditions electrical characteristics symbol parameter rating unit v cc power supply (v cc - gnd) 6 v t a operating ambient temperature -40 to +85 c t stg storage temperature -65 to +150 c symbol parameter rating unit v cc power supply (v cc - gnd) 3 to 5.5 v t a operating ambient temperature -40 to +85 c symbol parameter min typ max unit ibias range of programmable laser bias current - - 60 ma imod range of programmable modulation current - - 45 ma vih pecl input high - v cc - 0.95 - v vil pecl input low - v cc -1.75 - v i cc supply current - imod+ibias +15 -ma tr/tf rise/fall time - 200 - ps
CS6706 century semiconductor inc. page 5 of 8 product description the CS6706 consists of a laser bias generator with automatic power control, a modulation current driver, and slow start and safety circuits which shut down laser drive current when a fault is detected. laser bias driver and apc the laser power control function is realized by a feedback loop which sets the average photo-current of a monitor diode equal to the reference sink current at pin pin. the precise value is controlled by a resistor, r pinset which is connected between pin rpin and ground. setting procedure to apc control loop two external resistors r pinset and r dcb should be set as following procedures. (i). find out desired photo-current (i pd ) generated from monitor diode and associated bias current (i bias ) from i bias v.s. i pd curve. see figure 3 . (ii). then r pinset can be decided as r pinset = 1.06 / i pd . (iii). and r dcb can be decided as r dcb = 1.06 / [(i bias /214) - 130 a] figure-3 example of i bias v.s. i pd curve setting without apc control loop if the automatic power control function is not desired, for example in a vcsel application, simply replace the monitor diode by a 18k ? resistor and disconnect pin rdcb and pin basfb (please refer to application circuit schematic). the laser bias current will be i bias = 214 / r dcbset (5v) i bias = 210 / r dcbset (3.3v) 10.8 19.7 26.7 31.4 35.3 39.2 44.1 48.9 52.5 55.5 59.1 67.9 78.6 105 0 20 40 60 80 100 120 0 5 10 15 20 25 30 35 40 45 i bias (ma) i pd ( a)
CS6706 century semiconductor inc. page 6 of 8 modulation current driver the modulation current is adjusted by a resistor r modset which is connected between pin rmod and ground. i mod = 408 / r modset (5v) i mod = 394 / r modset (3.3v) rise/fall time adjustment the rise/fall time of the CS6706 can be adjusted by a resistor r ofsset connected between pin rofs and ground. safety circuits two window comparators are used to determine if the laser bias current is correct. if an abnormal condition is detected, the laser bias and modulation current will be shut down. in addition, the fail pin will output a logic high (cmos level) indicating a laser bias error has occurred. this error condition can only be reset by powering the CS6706 off. slow start during power up, the voltage on pin start reaches the supply voltage in a time determined by a time constant set by an on-chip resistor (25k ? ) and an off-chip capacitor. bias and modulation current can only begin when the voltage at the start pin exceeds 1/3v dd and 2/3v dd respectively.
CS6706 century semiconductor inc. page 7 of 8 package outline (tssop-20) symbol dimensions in millimeters dimensions in inches min nom max min nom max a- -1.2- -0.48 a1 0.05 - 0.15 0.002 - 0.006 a2 0.80 1.00 1.05 0.031 0.039 0.041 b 0.19 - 0.30 0.007 - 0.012 c 0.09 - 0.20 0.004 - 0.008 d 6.40 6.50 6.60 0.252 0.256 0.260 e - 6.40 - - 0.252 - e1 4.30 4.40 4.50 0.169 0.173 0.177 e - 0.65 - - 0.026 - l 0.45 0.60 0.75 0.018 - 0.030 0 -8 0 -8 l e e1 c e b a1 a2 a d
CS6706 century semiconductor inc. page 8 of 8 application circuit schematic figure-4 using tssop-20 package c3 10uf/16v c12 1uf vcc c5 0.1uf gnd r5 24 c7 0.1uf ld+ r11 47 tx- tx+ c8 0.1uf c2 0.1uf c4 0.1uf r2 r gnd r1 r gnd (tssop-20) gnd gnd pin r3 r ld- c10 0.1uf 1 2 3 u1 CS6706 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 dinn dinp vdd vss vref rmod rofs rpin rdcb basfb pin vdda vssa dcb modn vsso modp fail disable start r4 r c1 0.01uf c6 0.01uf gnd vcc pin r6 24 c11 0.1uf gnd
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